High resistivity silicon has been found to be well suited for radio frequency (“RF”) applications. In particular, high resistivity silicon has been found to reduce RF power loss which benefits the active and passive elements of an RF system and has been fount to improve isolation properties. Silicon on insulator structures (“SOI structures”) with high resistivity handle wafers are characterized by increased yield and increased device performance relative to high resistivity bulk silicon wafers.
Such SOI structures have applicability in a number of RF applications. For instance, SOI structures with high resistivity handle wafers may be used in high performance RF circuits with digital logic and memory on the same chip as reported by Fiorenza et al. in “RF Power Performance of an LDMOSFET on High-Resistivity SOT,” IEEE Electron Device Letters, Vol. 26, No. 1 (2005). LDMOSFETs built on high resistivity SOI structures have a variety of uses in integrated RF power applications including, for example, cellular phones, wireless LANs, fixed wireless and radiation hardened applications.
SOI structures built on high resistivity substrates may be formed by using a handle wafer produced from an ingot that was pulled from a silicon melt (of which the impurities therein may be counter-doped to increase resistivity) by the so-called Czochralski method. However it is difficult to reliably manufacture such handle wafers as trace dopant impurities in the polysilicon melt and/or crucible and the like may significantly shift the resistivity from the target value and the dopant impurities in the melt will vary in concentration as the crystal is pulled as the segregation coefficients of most dopant impurities are not equal to unity. Further, Czochralski grown silicon can have a relatively high interstitial oxygen concentration. During certain device processing steps, this oxygen can agglomerate and form thermal donors which affect the resistivity of the wafer. In addition, high resistivity handle wafers are susceptible to formation of a surface inversion layer near the dielectric layer (e.g., buried oxide layer). Methods to prevent inversion of the substrate surface (e.g., damaging the interface or using a layer of polysilicon at the interface) are generally undesirable as they are costly and add complexity to SOI manufacturing processing.
A continuing need exists for SOI structures that exhibit improved reliability and yield when used in RF applications and, in particular, high performance RF circuits. A continuing need also exists for methods for preparing such SOI structures and, in particular, which allow such structures to be manufactured in a reliable and cost-efficient manner.